Ambiq Micro Apollo3 Blue MCU TSMC 40 nm CMOS Process Digital Floorplan Analysis

Product Code

DFR-1907-802

Release Date

30/08/2019

Availability

Published

Product Item Code

AQM-1M

Device Manufacturer

Ambiq Micro

Device Type

Microcontrollers

Subscription

Logic

Channel

Logic - Digital Floorplan (IP)

Logic - Digital Floorplan

Ambiq Micro Apollo3 Blue MCU TSMC 40 nm CMOS Process Digital Floorplan Analysis

This report presents a Digital Floorplan Analysis of the AmbiqMicro Apollo3 die found inside the AmbiqMicro 1M microcontroller unit (MCU). The AmbiqMicro 1M MCU was extracted from the Huawei TER-B19 Band 3 Pro activity tracker.

This report contains the following detailed information:

Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
Scanning electron microscopy (SEM) plan-view micrographs showing the layout of the die at the levels including fin/STI, gate, contacts, and minimum pitch metals
Measurements of horizontal dimensions of some of the major layout features, particularly the pitch and track height of standard cells
Plan-view optical micrograph of the die delayered to the metal gate level
Identification of major functional blocks on a gate level die photograph
Table of functional block sizes and percentage die utilization
High-resolution top metal and gate level die photographs delivered in the CircuitVision Software
Cost of die and tested packaged die, based on the manufacturing cost analysis of the observed process

View Table of Contents

Related Analysis	Manufacturer	Analysis Type	Subscription Channel
TSMC S/D Architecture Evolution (Redacted)		Process	Logic - Transistor Architecture Comparison
Intel Gate Architecture Evolution (Redacted)		Process	Logic - Transistor Architecture Comparison
Qualcomm Snapdragon 888 A78 CPU SoC Design Analysis	Qualcomm	Process	Logic - SoC Design Analysis, Logic - SoC Design Analysis (IP)
Qualcomm SM8350 Snapdragon 888 Samsung 5 nm LPE CPU (X1) SoC Design Analysis	Qualcomm	Process	Logic - SoC Design Analysis, Logic - SoC Design Analysis (IP)
Intel Channel Architecture Evolution		Process	Logic - Transistor Architecture Comparison
Intel Source/Drain Architecture Evolution		Process	Logic - Transistor Architecture Comparison
Ambarella CV22 SoC Digital Floorplan Analysis	Ambarella	Floorplan	Logic - Digital Floorplan, Logic - Digital Floorplan (IP)
NVIDIA Ampere GA100 7 nm GPU Digital Floorplan Analysis	nVIDIA	Floorplan	Logic - Digital Floorplan, Logic - Digital Floorplan (IP)
Broadcom BCM56880 Trident 4 TSMC N7HPC Process Digital Floorplan Analysis	Broadcom	Floorplan	Logic - Digital Floorplan, Logic - Digital Floorplan (IP)
Intel Xe GPU DG1 Digital Floorplan Analysis	Intel	Floorplan	Logic - Digital Floorplan, Logic - Digital Floorplan (IP)