TSMC’s enhanced 3nm process, N3E, employs fewer double-pattered EUV layers and allows more flexibility in the number of transistor fins than its predecessor, N3.
A serdes transceiver from Eliyan allows 32Gbps bidirectional chiplet signaling. It can reduce system cost in some systems by eliminating interposers or reduce power by halving speeds with no net bandwidth change.
MediaTek’s new top-of-the-line smartphone processor upgrades to the latest cores and protocols, offering ray tracing and other new capabilities for premium-phone buyers.
Quadric’s Chimera DLA IP executes both neural-network code and application code. Ranging from 1 to 16 TOPS, it blends the functions of a CPU, a DSP, and a DLA.
Andes is taking its RISC-V lineup to the next level with the AX60 family, which uses a quad-issue out-of-order microarchitecture to double CPU performance relative to the earlier AX40 family.
Aim Future’s AI accelerator IP targets performance ranging from 32 GOPS to 16 TOPS. It optionally offers the ability to perform incremental learning at the edge.
Nvidia has revised its automotive roadmap, replacing the product code-named Atlan with the new Thor processor, which targets an impressive 2,000 trillion operations per second (TOPS).
Ceva’s PentaG-RAN is a baseband IP block for cellular infrastructure. Packing multiple fixed-function units and two DSP types, it targets SoCs for RUs, DUs, small cells, and beam-forming chips.
Arm’s next Neoverse CPU, code-named Demeter, will appear in Nvidia’s Grace processor in 2023, matching the single-thread performance of mainstream Xeon products for the first time.
Seven years after releasing LiquidSecurity, Marvell has unveiled a second-generation PCIe card that increases RSA throughput by 20% and ECC throughput tenfold.
STMicroelectronics’ new SR6P7x and SR6P6x automotive SoCs aggregate low-level ECUs into domains or zones. With a novel choice of nonvolatile memory for code, the company has a strong focus on deterministic real-time performance.
Nvidia’s newest gaming GPU, code-named Ada Lovelace, builds on the Ampere design with faster clock speeds, far more cores, a massive cache memory, and faster ray tracing.
Having closed its Xilinx acquisition, AMD is launching a new FPGA with much more CPU power than previous members of its Versal family, targeting it at 400Gbps smart NICs.