Ceva XC20 Enables Vector-Unit Sharing

The new Ceva XC20 architecture implements simultaneous multithreading in a vector DSP. The first product to use it, the XC22 more than doubles area efficiency compared with Ceva’s previous DSP cores.
Joseph Byrne
Joseph Byrne

Ceva’s XC20 vector-DSP architecture implements a new simultaneous multithreading technique, allocating the resources of a single vector unit to two threads instruction by instruction. Vector-unit utilization increases, boosting the licensable DSP’s area efficiency. Combined with other updates, Ceva reports the first XC20-based core, the dual-thread XC22, is more efficient than the single-thread XC4500 and the dual-thread XC16.

Sporting 128 multiply-accumulate (MAC) units, the XC22’s vector performance slots it between the 64-MAC XC4500 and the 256-MAC XC16. The XC4500 divides its MACs between two vector computation units (VCUs), and the XC16 divides its resources among four VCUs. The XC22, by contrast, has a single VCU.

Although the XC16 and the XC22 both process two threads, having dedicated scalar resources and sharing vector computation units (VCUs), the XC22’s approach is easier to harness and more flexible. Before, software could allocate a VCU to one thread or another at run time. Now, however, software needn’t explicitly assign a VCU to a thread; an arbitration unit in the DSP manages sharing.

Threads, moreover, can share resources in a VCU, whereas the XC16 allocated a whole VCU to a thread. Compared with the two threads and 128 MACs afforded by dual XC4500 instances, the XC22 has the added benefit that a single thread can potentially claim all 128 when necessary. Therefore, the XC22’s sharing approach is more like the function-unit sharing in a dual-thread x86 CPU than in the XC16.

Unlike the XC16, a beefy DSP that has four VCUs and is best suited to 5G infrastructure, the XC22 targets a broader market: Ceva positions it for high-end user equipment (e.g., smartphone modems) and mobile infrastructure. For infrastructure, it would handle physical-layer and digital-front-end functions in distributed units (DUs) and radio units (RUs). Planned for 3Q23, the design’s general availability will coincide with the freeze of 5G Advanced (3GPP Release 18). Ceva already claims a Tier One OEM as a licensee.

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