Lattice Details First Avant FPGAs
Avant-E is the first series based on Lattice’s Avant platform, announced in 2021. It addresses the FPGA midrange with devices that have logic and security but no CPUs.
Lattice Semiconductor’s Avant-E family includes three chips targeting low-power midrange FPGA designs. It moves the company into new territory, offering greater logic density than its predecessors.
Lattice announced the Avant platform in 2021 as a density increase from the smaller legacy chips it brands as the Nexus platform. It’s had success in low-density designs to which the major vendors rarely pay attention, and it’s betting it can move into a higher-density range that has stagnated in the last decade. Microprocessor Report defines that midrange as roughly 50,000–500,000 logic cells (LCs), an approximation given that LCs differ by architecture. Avant-E is the first Avant family Lattice has detailed.
The new architecture is typical for a general-purpose FPGA. It has a central fabric comprising four-input lookup tables (LUTs), block RAM, and DSP slices; programmable I/Os; a DRAM interface; and serdes blocks. Lacking hard CPUs, it’s not an SoC FPGA. In addition, a hard-coded security block includes a crypto engine, anti-tamper features, and a physically unclonable function (PUF) to give each chip a unique ID. The company says it’s working with security researchers to implement new quantum-resistant cryptography algorithms in programmable logic and to harden critical circuits for postquantum algorithms such as Dilithium. Although available in standard BGA packages, Lattice is offering small packaging as well.
Sampling now with general availability scheduled for midyear, the three Avant-E units range from roughly 200,000 to 500,000 LCs. DSP slices and block RAM scale linearly with logic. The 18x18 DSP slices are fracturable into four 8x8 DSPs for AI designs, which commonly work with INT8 data.
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