Obtained through its Xilinx acquisition, AMD’s RFSoCs meld FPGA and processor functions with blocks for mobile infrastructure. The ZU64DR and ZU63DR join a line of RFSoCs that implement DFE functions.

Intel’s Ponte Vecchio data-center GPU is a packaging tour de force. Available in three models, it delivers leading FP64 vector performance.

Avant-E is the first series based on Lattice’s Avant platform, announced in 2021. It addresses the FPGA midrange with devices that have logic and security but no CPUs.

The new Xeon W-2400 and W-3400 processors integrate 6 to 56 CPUs and support DDR5 as well as PCIe Gen5, providing a needed upgrade to Intel’s workstation line.

Targeting IoT, wearables, consumer electronics, and robotics, Alif Semiconductor is building microcontrollers that consume less than 1 W and provide up to 250 GOPS using Arm Cortex CPUs and Ethos AI units.

Apple’s new M2 Pro and M2 Max offer more CPU, GPU, and AI performance than their predecessors, helping the company maintain its differentiation.

Two years into his tenure, CEO Pat Gelsinger continues to oversee major product delays. As profits fade, he must consider axing some of the company’s emerging businesses to meet expense targets.

A new startup, Rapid Silicon, is entering the FPGA market. Its Gemini SoC FPGAs, with hardened CPUs, compete against aging midrange alternatives from AMD, Intel, and Microchip.

MPR’s analysts have developed forecasts for various processor markets. The trend toward PC processors with AI accelerators is under way. Meanwhile, some AI-accelerator startups will topple as their funding runs out.

AMD’s MI300 accelerator will compete with Nvidia's Grace Hopper in the HPC and AI markets. It uses AMD's third-generation CDNA3 architecture and features x86, GPU, and memory die in a single package for improved performance.

Qualcomm’s Ride Flex SoC combines ADAS and cockpit applications, integrating workloads that have no safety criticality with those requiring ASIL B and ASIL D safety.

TSMC presented papers at IEDM detailing its 3nm N3 and N3E processes. N3 reduces CPP by 6nm compared with N5. SRAM cells are no smaller in N3E than in N5.