Blue Cheetah Connects Chiplets

Proprietary technology helps startup Blue Cheetah rapidly create custom die-to-die interconnects, including analog circuits, to attach chiplets. Focusing on the BoW standard, the company supports two fab processes.
21Nov

TPUv4 Adds Large On-Chip Memory

The TPUv4 is now generally available through Google Cloud, although the company has used it internally for a year. The ASIC doubles the number of matrix units relative to the TPUv3.
21Nov

Eliyan Doubles UCIe Bandwidth

A serdes transceiver from Eliyan allows 32Gbps bidirectional chiplet signaling. It can reduce system cost in some systems by eliminating interposers or reduce power by halving speeds with no net bandwidth change.
14Nov

Andes AX65 CPU Targets Data Center

Andes is taking its RISC-V lineup to the next level with the AX60 family, which uses a quad-issue out-of-order microarchitecture to double CPU performance relative to the earlier AX40 family.
07Nov

Nvidia’s Thor Hammers Atlan

Nvidia has revised its automotive roadmap, replacing the product code-named Atlan with the new Thor processor, which targets an impressive 2,000 trillion operations per second (TOPS).
31Oct