This report presents a Power Floorplan analysis of the Exagan EXA06C065LDS0 power gallium nitride (GaN) FET.
This report contains the following detailed information:

• Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
• SEM cross-sectional micrographs of the general structure of the die dielectric materials, major features, and transistors
• Measurements of vertical and horizontal dimensions of major microstructural features
• Plan-view optical micrograph of the die delayered to the polysilicon layer
• Identification of major functional blocks on a polysilicon die photograph
• Table of functional block sizes and percentage die utilization
• High-resolution top metal and polysilicon die photographs delivered in the CircuitVision software
• Cost of die and tested packaged die, based on the manufacturing cost analysis of the observed process