This report presents a power floorplan analysis of the STMicroelectronics MASTERGAN1 device. The MASTERGAN1 features a 600 V, 150 mΩon-resistance half-bridge circuit with gallium nitride high electron mobility transistors with a 650 V drain-source breakdown voltage (V(BR)DS), and a silicon-based bipolar-CMOS-DMOS gate driver [1]. The focus of this report is on the GaN HEMT dies.