NXP Semiconductors PCIMX7U5DVP08SC (i.MX 7ULP Family) Ultra-Low-Power Application Processor Samsung 28 nm FDSOI Process Digital Floorplan Analysis

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Logic - Digital Floorplan
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This report presents a Digital Floorplan Analysis of the NXP N54W die found inside the Freescale PCIMX7U5DVP08SC component.

This report contains the following detailed information:
  • Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
  • Scanning electron microscopy (SEM) plan-view micrographs showing the layout of the die at the levels including, fin/shallow trench isolation (STI), gate, contacts, and minimum pitch metals
  • Measurements of horizontal dimensions of some of the major layout features, particularly the pitch and track height of standard cells
  • Plan-view optical micrograph of the die delayered to the gate level
  • Identification of major functional blocks on the gate level die photograph
  • Table of functional block sizes and percentage die utilization
  • High-resolution top metal and polysilicon level die photographs delivered in the CircuitVision software
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