Product Item Code
Logic - SoC Design Analysis
This project presents a Standard Cell Essentials Analysis of the NVIDIA Titan V (GV100) application processor, built in TSMC’s 12 nm high-k metal gate (HKMG) finFET CMOS process. This analysis is focused on the tensor core area. We have assessed the standard cell architecture by extracting and locating in the tensor core layout multiple standard cells. We have extracted the routing density of the tensor core digital logic library. Process and back end of line (BEOL) stack-up and utilization have also been analyzed.
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