Samsung and TSMC are forging ahead with 3 nm and 2 nm silicon processing as well as 3D-packaging technologies. Globally dispersed fab construction continues for old and new nodes.
Semidynamics’ new Atrevido 423 CPU brings the company into RISC-V competition with other four-issue licensable cores. Deep customizability and the Gazzillion memory-request queue remain the primary differentiators.
The customizable Tensilica Xtensa LX8 adds an L2 cache and branch-target buffer to boost performance. An improved DMA engine should increase performance on AI and other applications.
Kalray's Coolidge v2 chip targets network processing for the storage market. It’s based on the company’s massively parallel processor array (MPPA) architecture; it’ll enter production in 2024.
Ambiq’s Apollo4 Lite and Blue Lite target lower-cost fitness bands that require less graphics and display processing. Power is less than that of competitors, although pricing is higher.
Bosch, Infineon, Nordic, NXP, and Qualcomm are investing in a joint venture to advance RISC-V. Initially focusing on the automotive industry, the venture could address RISC-V’s fragmentation and accelerate its adoption.
Intel’s proposed x86-S instruction set removes several legacy features, simplifying CPU designs but breaking compatibility with some old software. We expect it to debut in processors in 2025.
Security blocks performing similar functions may have different names depending on the context or industry; some of them are losing their specific meanings. A survey of alternatives allows us to sharpen understanding and communication.
Intel’s new APX extension adds registers and other features to the instruction set, and AVX10 will enable the company’s little CPUs to support the same vector-processing operations as its performance cores
Yet another South Korean AI chip startup, Deepx, has emerged from stealth mode. The company’s products target computer-vision applications and provide performance from 2 to 184 TOPS.
Neo’s 3D X DRAM technology promises an 8× increase in DRAM capacity with a per-bit cost one-sixth that of conventional DRAM. The company seeks a partner for silicon implementation.
TechInsights’ floorplan analysis reveals MediaTek and Qualcomm have increased GPU size in their flagship smartphone processors while Apple has held its GPU size constant.
At the recent VLSI Symposia, Intel presented three papers discussing PowerVia technology: one on the technology itself, another on the results from a test microprocessor, and a third looking at the possible evolution of PowerVia.
Bluespec’s licensable RISC-V MCUX CPU IP adds custom instructions to its existing ultralow-footprint CPU, branded MCU. Optimized for FPGAs, these CPUs occupy fewer lookup tables than any other commercial RISC-V core.
Tesla has started deploying its Dojo supercomputer that employs unusual technologies to pack AI-training performance in a smaller volume than Nvidia-based systems.
