Synopsys Joins RISC-V Bandwagon
Author: Bryon Moyer
Synopsys has joined the RISC-V movement by adding an ARC-V licensable CPU product line to its existing CPU IP portfolio. The preproduction announcement covers a broad range of capabilities from ultra-low-power to higher performance that allows multiple coherent clusters.
ARC-V (pronounced “ark-five”) comprises three families that address small, embedded designs, more powerful real-time designs, and higher-end embedded designs. The lattermost supports OSes such as Linux, but the company isn’t targeting smartphone or server applications; it’s focused on embedded designs only.
Aside from the instruction set, the new models are similar to the latest ARC cores; selective microarchitecture enhancements should boost performance above that of the existing cores. Synopsys will continue to offer the traditional ARC CPUs alongside the new ARC-V models; it hasn’t indicated whether the traditional ARC CPUs will receive similar upgrades in the future.
Synopsys has licensed ARC CPU intellectual property (IP) using its proprietary architecture since 2010. It says it has been watching RISC-V’s progress and—based on customer requests and the growing strength of the RISC-V ecosystem—it’s time to jump in. This leaves Cadence and Arm as the only major CPU licensors without a RISC-V offering.
The three CPU families comprise a 32-bit RMX family for the smallest, most power- and cost-sensitive designs, a 32-bit RHX family for larger higher-performance real-time systems, and a 64-bit RPX family for the largest designs. The RMX models have DSP extensions; the two larger families offer vectors and custom instructions as an option. Both the RHX and RPX families have multicore versions; the RPX includes a Chi port for SoCs requiring multiple coherent CPU clusters. RTL design is ongoing; the RMX family is scheduled for general availability Q2 2024, although thorough verification could push that date out. The RHX and RPX families are planned for availability in the second half of 2024.
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