MediaTek’s newest smart-TV processor targets high-end 4K screens that display up to 120 frames per second (4K120). It features AI-enabled upscaling and can display eight video streams at once.
Joseph Byrne is now editor-in-chief of Microprocessor Report, replacing Linley Gwennap. Linley will continue as editor emeritus, serving on the editorial board and contributing articles.
Arm and Qualcomm are locked in an ugly public spat over the rights to Nuvia’s CPU. Unresolved, this conflict could hamper Arm’s progress in the PC market and foment interest in RISC-V.
Accompanying the launch of the new flagship Snapdragon are game titles employing its marquee new graphics feature, ray tracing. SoC-architecture updates promise better-looking pictures.
ZeroPoint’s Ziptilion-BW IP can raise an application’s performance, lower its power, and increase the apparent memory size. But doing so effectively depends on data patterns.
AMD’s fourth-generation Epyc takes server processors to a new level, delivering 50% gains in core count, memory bandwidth, and I/O speed relative to the previous generation
Proprietary technology helps startup Blue Cheetah rapidly create custom die-to-die interconnects, including analog circuits, to attach chiplets. Focusing on the BoW standard, the company supports two fab processes.
Chiplet use is increasing, primarily for large in-house computing projects, but small chip designs don’t benefit. A broad third-party chiplet market remains years away.
The TPUv4 is now generally available through Google Cloud, although the company has used it internally for a year. The ASIC doubles the number of matrix units relative to the TPUv3.
TSMC’s enhanced 3nm process, N3E, employs fewer double-pattered EUV layers and allows more flexibility in the number of transistor fins than its predecessor, N3.
A serdes transceiver from Eliyan allows 32Gbps bidirectional chiplet signaling. It can reduce system cost in some systems by eliminating interposers or reduce power by halving speeds with no net bandwidth change.
MediaTek’s new top-of-the-line smartphone processor upgrades to the latest cores and protocols, offering ray tracing and other new capabilities for premium-phone buyers.
Quadric’s Chimera DLA IP executes both neural-network code and application code. Ranging from 1 to 16 TOPS, it blends the functions of a CPU, a DSP, and a DLA.
Andes is taking its RISC-V lineup to the next level with the AX60 family, which uses a quad-issue out-of-order microarchitecture to double CPU performance relative to the earlier AX40 family.
