Eliyan Doubles UCIe Bandwidth
A serdes transceiver from Eliyan allows 32Gbps bidirectional chiplet signaling. It can reduce system cost in some systems by eliminating interposers or reduce power by halving speeds with no net bandwidth change.
Startup Eliyan has developed a serdes transceiver that permits bidirectional signaling across a wire at 32Gbps. Applied to the UCIe chiplet-interconnect protocol, some chiplet assemblies that would otherwise require expensive advanced packaging can employ conventional organic package substrates instead.
Bidirectional signaling allows a reduction in the wire count by consolidating transmit (Tx) and receive (Rx) lines. Alternately, the same number of wires can run at half the data rate in each direction, simplifying Tx and Rx circuits. Eliyan’s interface circuitry, which it brands NuLink, is proprietary, but the company hopes to offer bidirectional UCIe signaling to JEDEC for standardization toward the end of the year.
Cofounder Ramin Farjadrad is both CEO and CTO. He has a deep communications background, having implemented PAM4 in silicon in the late 1990s, before the industry was ready to accept it. He cofounded Aquantia, a maker of high-speed transceivers that Marvell acquired, implementing the first Bunch of Wires (BoW) chiplet-interconnect interface. Syrus Ziai serves as VP of Engineering. The company completed a $40 million Series A funding round last March, led by Tracker (the venture arm of Cerberus Capital Management); Celesta Capital, Intel, and Micron were among the strategic investors.
The transceiver intellectual property (IP) and a silicon proof of concept are scheduled for availability in 1H23. Additionally, Eliyan plans to offer a gearbox device for expanding the number of High Bandwidth Memory (HBM) chips that can link to an SoC. Branded NuGear, that product is expected to tape out in roughly the same timeframe, with availability scheduled for 2024.
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