N3E Will Be TSMC’s Main 3nm Node
TSMC’s enhanced 3nm process, N3E, employs fewer double-pattered EUV layers and allows more flexibility in the number of transistor fins than its predecessor, N3.
Sometimes it’s better to sell the sizzle than the steak. As its N3 technology nears production, TSMC has begun disclosing details about subsequent 3nm variations and a 2nm node as well as glimpses at future technologies they could incorporate.
Recent months have clarified that N3E will be TSMC’s mainstream 3nm process, targeting a wave of customers following the N3 early adopters. The foundry avoids comparing N3 and N3E, but we can from public statements glean that the latter reduces cost compared with the former and that performance, power, and area (PPA) are slightly worse. Scheduled to enter volume production in 2H23, compared with the end of 2022 for N3, the new process comes three years after N5. It will account for just a “mid-single-digit percentage” of wafer revenue in 2023, according to the company.
In its 3Q22 earnings call, TSMC reiterated that N3 was on track for end-of-year volume production with high yield and for ramping shipments into smartphones and high-performance computing (HPC, likely including any high-speed design). Also during the call, the foundry noted that wafer demand exceeds its capacity owing to a fab-tool shortage. It will be at maximum capacity through 2023. Most customers will choose N3E, indicating cheaper wafers are worth waiting for.
TSMC plans to follow N3E with N3P and then N3X, each delivering an incremental speedup. We speculate they’ll derive from N3E, but to attract N3 customers seeking mid-cycle refreshes, their PPA can’t regress. Then, in 2025, the foundry plans to launch N2. Although it comes two years after N3E, that node offers only incremental transistor-density increases, owing largely to backside power. Power consumption should decline thanks to gate-all-around (GAA) transistors. Research into other technologies is paving the way to future enhancements.