SiFive P470 Adds Vectors to Midrange
SiFive’s P400 series CPUs deliver midrange performance in a little-core footprint. The three-way out-of-order design includes an optional vector unit.
SiFive has added two efficiency-focused CPUs to its RISC-V fleet. The new P450 and P470 complement the performance-tuned P650 announced last December. Further expanding the company’s application-CPU family, SiFive also added a vector unit to the P650, calling the resulting product the P670. By supporting a common RISC-V profile and extensions, the P400- and P600-series together give customers a choice between big and little CPUs, mirroring the CPU pairings of Arm, Intel, and Apple. SiFive plans to release production-quality P400 RTL in 1Q23. The company presented the P400 series at the Linley Fall Processor Conference (powered by TechInsights).
To design the P450, the company took a scalpel to its erstwhile flagship P550. It trimmed the fetch and decode width, cut out execution pipelines, and pared down resources such as physical registers and the reorder buffer. It then updated the decoders and other logic to make them compatible with the P650. The result is a compact three-way superscalar design that executes instructions out of program order and runs at up to 3GHz in a 7nm process. The P470 adds a vector unit to the design.
Considering SiFive’s whole portfolio, the P400-series is midrange, delivering more integer performance than the older P270 and Essential U-series but less than the P600-series. Although it adds a SIMD unit, the P470 remains a general-purpose core. For customers focused on number crunching, SiFive still offers the X200 CPUs, which implement wide vector units and special AI instructions.
We foresee the P400 CPUs appearing in designs similar to those that employ Cortex-A55 or Cortex-A53 for application processing and in designs that can get by with a smaller software ecosystem. Examples include designs where the licensee and its OEM customers provide all software and have smaller code bases that they develop or port themselves. Other possible designs could host applications that are built in Java or otherwise aren’t natively compiled.