NVIDIA GB10 Superchip CPU Analysis: Inside the MediaTek CPU Die Powering DGX Spark

Understanding the CPU design choices, performance implications, and architectural trade-offs within NVIDIA's GB10 Superchip.

NVIDIA's GB10 Superchip is a notable departure from traditional AI accelerator design. Rather than relying solely on in-house compute technology, NVIDIA has integrated a MediaTek-designed CPU die alongside GPU and other compute elements within a single package. As AI infrastructure platforms become increasingly heterogeneous, understanding the architecture and design strategy behind this CPU is critical for system architects, infrastructure planners, and competitive intelligence teams.

Figure 1 – TechInsights examines the die architecture, functional layout, and manufacturing process of the MediaTek AHJ11488B CPU die extracted from NVIDIA's GB10 superchip (Source: TechInsights)

NVIDIA's CPU Strategy for AI Infrastructure

The CPU component plays a significant role in determining how effectively the GB10 Superchip can support AI and high-performance computing workloads. A key question is whether this processor was purpose-built for NVIDIA's AI infrastructure strategy or adapted from an existing MediaTek design.

To answer that question, TechInsights conducted a detailed reverse-engineering analysis of the MediaTek AHJ11488B CPU die extracted from the NVIDIA DGX Spark desktop computer. Through physical deconstruction and microscopic inspection, the analysis examines the die architecture, functional layout, and manufacturing approach used within the CPU.

What the Die Reveals

The analysis shows a highly utilized design, with 78% of the die area occupied and 59% dedicated to digital logic and memory. The CPU integrates ten ARM Cortex-X925 performance cores and ten ARM Cortex-A725 efficiency cores, supported by substantial L3 cache, LPDDR5x memory interfaces, PCIe connectivity, and dedicated chip-to-chip interconnect logic.

Physical analysis provides valuable insight into architectural priorities, but critical questions remain. Is the CPU optimized specifically for AI infrastructure workloads? What manufacturing trade-offs were made to balance performance, power efficiency, and cost? How does the design compare with competing approaches in the emerging AI systems market?

Answering these questions requires process technology characterization, gate-level measurements, and memory cell analysis. These data points form the foundation for estimating performance potential, power efficiency, and manufacturing economics.