Winbond 20 nm DRAM Memory Floorplan Analysis

Analysis of Winbond JAA123 20nm DRAM die in W664GG6RB-06 DDR4 package, featuring BCAT structure and detailed array-periphery layout for 4Gb density.

Winbond JAA123 die was found inside Winbond W664GG6RB-06 package that features one 4 Gb DDR4 die. The JAA123 die was manufactured by Winbond using its 20 nm generation stacked DRAM CMOS process, incorporating bit line under capacitors and a buried word line forming the gate of the buried cell array transistor (BCAT). The JAA123 die has its memory arrays arranged into two halves separated by a central horizontal circuit strip. For each array area half, memory arrays are grouped into two 2x2 array banks, each contains 4 memory arrays separated by local row and column address path and local datapath circuit blocks. The central horizontal circuit strip contains the main peripheral circuitry, including most of the global datapath, address path, voltage generating, and control circuitry.