Embedded & Emerging Memory competitive insights to inform your business strategy
The TechInsights Embedded and Emerging Memory Subscription provides companies with competitive analysis revealing the process design innovations of today’s technology market leaders.Request a demo
As the industry has been developing several next generation memory types, technologists are driven to accelerate development and optimize process steps on new device releases.
Combined with our 30+ years of expertise as well as extensive breadth of analysis and technology, a TechInsights subscription can help inform business strategy by delivering curated, competitive insight on cutting edge technical innovation.Download a subscription overview
The following channels are available in the Embedded and Emerging Memory subscription:
- Floorplan Analysis (MFR): Focused on embedded and emerging memory, provides a high level view of design quality by providing insight into memory area efficiency, the technology node for process generation, and memory capacity per die through functional analysis and benchmarking. Analysis may include process node and foundry identification, critical dimensions, functional block summary, stacked optical top metal and poly die photo delivered in CircuitVisionTM, SEM bevel and/or cross-sectional imaging
- Process Analysis: Focused on enabling understanding of all process aspects of embedded and emerging memory through dimensional, materials, architecture analysis. Also provides analyst perspective on the above to provide insight into trends and roadmap. Analysis may include SEM cross-sectional and bevel imaging, TEM cross-sectional with TEM EDS, technical trend/roadmap by technology element, interaction analysis, detailed explanation of process integrations and/or next node predictions
- Process Flow Analysis: Provides insight into the manufacturing process steps, materials, and technology across leading edge embedded and emerging memory chips. Requires a subscription to the Embedded & Emerging Process channel.
- Process Flow Analysis: Spreadsheets showing process architecture, mask list, and integration-level process steps
- Process Flow Full Emulation: Layout GDS fully decomposed into process layers, Synopsys Process Explorer PDF output reports, and/or Synopsys Input (Route-Level Deck) [Requires Synopsys license to view and modify]
TechInsights’ analysis combined with our analyst expertise
Cell design technology interaction analysis
Detailed explanation of process integration from wafer-in through wafer-out
Process steps, materials, equipment type, unit process
SEM and TEM cross-sectional and top-view images
Layer annotations, specific process module, assumption
Support on analysis related questions
The authoritative and most cost-effective source of reliable and accurate analysis
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