The Chip Insider®– IBM’s NanoStack Transformational or just another CFET

Summary:

A week ago, Thursday, I was knocked out of my seat with this transistor cartoon on LinkedIn… posted by Dr. Huiming Bu, Vice President and head of IBM Semiconductors Global R&D and Albany Operations, with this covert lead in: “They say a picture is worth a thousand words. I saw one three years ago.” It turns out, IBM was getting ready to launch a revolutionary new transistor architecture … that could obsolete two decades and billions of dollars of research into the monolithic CFET.

The cartoon reminded me of when IBM did exactly the same thing in the 1990s with electroplated copper interconnect… Intel’s Tri-gate FinFET in 2002… IBM’s NanoStack has obvious electrical and manufacturing advantages. If you knew anything about transistor architecture and saw this, it had to be a ‘Why didn’t I think of that?’ moment.

The key differences to note are 1) It’s far simpler with only… 2) This makes it possible to… 3) The transistors are staggered, so … 4) The purplish-grey slice through the middle is a bonding layer, not a grown dielectric. Seeing the last was a ‘is that what I think it is?’ moment, which …

Item 4 is most critically important, because it means it’s a no-compromise stacked FET. No compromise because, the N- and P-type FETs can be independently optimized … To be fair, I’ve never liked the monolithic CFET as even I could see this structure would be a bear to build. Monolithic CFETs are not an easy trip to the build-a-bear semiconductor equipment store (not to be confused with the Build-A-Bear Workshop®)... with a monolithic CFET, one must …

Now, I’m just an economist, so don’t trust me writing the GAA is not a quick walk in the park. Consider that IBM first revealed its NanoSheet GAA transistor invention 2014… Realistically, it took more than 10 years.

As for the CFET, CEA-Leti was the first to propose the concept around 2006… IBM started 3D FET research in the same year they announced NanoSheets in 2014... IBM, imec, TSMC, Intel, and Samsung have all worked on it. Though IBM actually gave up on the concept in early 2024, putting all its resources into its NanoStack.

IBM’s progress has been faster than AI jumping from CPUs to GPUs. Its first paper announcing … That’s two years versus twenty for CFETs. NanoStack is targeted at the 7-angstrom node. They’ve demonstrated a chip with 100B transistors, which is twice the density of its 2nm NanoSheet device introduced five years ago in 2021. IBM’s research papers show a performance improvement of 50% higher, or an energy efficiency gain of 70%...

Overall, IBM's stacked and staggered polylithic architecture is a significant improvement over the monolithic CFET. With the latter, both transistors must be vertically aligned. Theoretically, it should be a smaller cell. In reality, this is not the case… IBM’s NanoStack transistor is a game changer because it extends the semiconductor roadmap visibility out to somewhere between 2040 and 2050. They show 2040, using the old 2-year cadence per node. A 3-year cadence puts us nearer to the 2050s.

“If you don’t like what’s being said, change the conversation” — Don Draper, Mad Men