SK hynix H25GTD0 321-Layer (V9) 1 Tb TLC 3D NAND Process Flow Analysis: Examining SK hynix's First 321-Layer 3D NAND Architecture

TechInsights first uncovered SK hynix's H25GTD0 in early 2026, documenting the industry's first commercially realized 300+ layer NAND product. That initial teardown provided a first look at SK hynix's ninth-generation (V9) 321-layer (321L) triple-level cell (TLC) 3D NAND architecture.

Since then, we have continued to examine SK hynix’s V9 architecture. After completing a Memory Floorplan Analysis, we have expanded our research with a NAND Full Process Essentials (NPF) analysis that combines analyst observations with SEM, TEM, TEM-EDS, and TEM-EELS characterization to examine the device's process implementation.

Figure 1 – TechInsights' latest process analysis examines SK hynix's first 321-layer V9 TLC 3D NAND, revealing its architecture and structural implementation. (Source: TechInsights)

A Closer Look at SK hynix's V9 Architecture

Our initial work documented SK hynix's transition from its 238-layer V8 architecture to a 321-active-wordline design built on a triple-stack integration scheme while retaining the company's peripheral circuit under cell array (PUC) architecture. It also measured a 1 TB memory capacity, a bit density of 23.52 Gb/mm², and a die seal area of 43.54 mm².

The latest analysis examines the device in greater detail. It documents the 321 active word lines, five metallization levels, and a triple-deck memory array with 346 total gates across the lower, middle, and upper decks. The analysis shows how SK hynix extended its 238-layer V8 architecture into the 321-layer V9 generation, documenting both the architectural features that were retained and the structural changes introduced in the newer device.

What the Full Process Analysis Includes

The NAND Full Process Essentials analysis combines analyst observations with detailed process characterization, including:

• SEM cross-sections along the word line (WL) and bit line (BL)
• TEM cross-sections with TEM-EDS and TEM-EELS analysis
• Memory array and memory array edge analysis
• Periphery analysis at the polysilicon level
• Package photographs, X-rays, and die photography

This analysis provides chip materials and capital equipment suppliers, chip fabrication and chip designers, and downstream markets with the technical evidence needed to benchmark SK hynix's latest NAND process technology and evaluate its manufacturing approach.