Logic Scaling for the Next Decade – Module 0: Introduction to the Series

Intro presentation launches the Logic Scaling video series, tracing device scaling from planar transistors to CFETs and 2D devices through the 2030s.

This presentation is an introduction to the seven-part video series Logic Scaling for the Next Decade, in which we analyze logic scaling beginning with planar devices and forecasting out into the 2030s with CFETs and 2D Devices. The series covers the reduction of physical dimensions, the introduction of novel materials and other performance enhancements, and the design technology co-optimization (DTCO). It explores the scaling of each area of a system-on-chip (SoC) die individually: logic, SRAM, and analog and I/O. The series ends with a high-level roadmap out to 2037 and general conclusions.