Nuclei Systems, a Chinese RISC-V processor vendor, announced a licensable RISC-V CPU core certified for ASIL D automotive applications, the most stringent level.
Arm’s new licensable Neoverse CSS N2 provides an entire compute subsystem implemented and verified on TSMC’s 5 nm process. It may save customers months of work.
Israeli startup Inuitive has released the NU4100 chip for 3D image processing. Incorporating the company's image-processing accelerators and technology from Arm and Synopsys, the chip targets autonomous machines, AR/VR, and the smarthome market.
Intel plans to introduce two server processors in 2024, Granite Rapids and Sierra Forest, using chiplets to boost the number of CPUs and deliver new DRAM and I/O capabilities.
Silicon Labs’ EFR32G23 and -28 support Amazon’s Sidewalk protocol. One transmits using subGHz FSK; the other FSK and Bluetooth. The company provides the full software stack.
Ceva’s updated NeuPro-M artificial-intelligence accelerator can better handle floating-point and INT4 data, enabling developers to use different types at different neural-network layers to improve performance with less impact on accuracy.
Samsung and TSMC are forging ahead with 3 nm and 2 nm silicon processing as well as 3D-packaging technologies. Globally dispersed fab construction continues for old and new nodes.
Semidynamics’ new Atrevido 423 CPU brings the company into RISC-V competition with other four-issue licensable cores. Deep customizability and the Gazzillion memory-request queue remain the primary differentiators.
The customizable Tensilica Xtensa LX8 adds an L2 cache and branch-target buffer to boost performance. An improved DMA engine should increase performance on AI and other applications.
Kalray's Coolidge v2 chip targets network processing for the storage market. It’s based on the company’s massively parallel processor array (MPPA) architecture; it’ll enter production in 2024.
Ambiq’s Apollo4 Lite and Blue Lite target lower-cost fitness bands that require less graphics and display processing. Power is less than that of competitors, although pricing is higher.
Bosch, Infineon, Nordic, NXP, and Qualcomm are investing in a joint venture to advance RISC-V. Initially focusing on the automotive industry, the venture could address RISC-V’s fragmentation and accelerate its adoption.
Intel’s proposed x86-S instruction set removes several legacy features, simplifying CPU designs but breaking compatibility with some old software. We expect it to debut in processors in 2025.
Security blocks performing similar functions may have different names depending on the context or industry; some of them are losing their specific meanings. A survey of alternatives allows us to sharpen understanding and communication.
Intel’s new APX extension adds registers and other features to the instruction set, and AVX10 will enable the company’s little CPUs to support the same vector-processing operations as its performance cores
