This report presents an Overhead SoC Design Analysis of the Apple A14 Bionic APL1W01 DDR I/O and logic region, built in TSMCs N5 high-k metal gate (HKMG) FinFET CMOS process. It is a collection of SEM montage images showing the transition between an I/O IP block and a digital logic block, showcasing the relationship to system-on-chip (SoC) design rules used on the Apple A14 Bionic APL1W01

The report includes

• Downstream product features and SoC-level areas of analysis
• Technology node contact and back-end-of-line (BEOL) process architecture assessment with stack up dimensions
• Features and dummy structures of the system-on-chip (SoC) design overhead associated with the transition between design IP blocks
• Scanning electron microscope (SEM) montage of a planar sample area delivered in CircuitVision
• Target areas are typically transitions between different types of IP blocks, such as analog I/O to digital, or to memory, and typically contain many dummy features
• Standard cell architecture by extraction and placement of multiple standard cells in the TB3 I/O logic layout
• Routing density of the TB3 I/O logic digital logic library