This report presents a Power Floorplan Analysis (PFR) of the Infineon IGI60F1414A1LAUMA1 600V half-bridge integrated CoolGaN HEMT. This is Infineon’s first GaN Integrated Power Stage (IPS) product where two GaN HEMTs plus silicon controller die are included within the same discrete package. An additional on-chip coreless isolation technology guarantees robustness from fast switching transients. It is suitable for power ranges from 30-500 W enabling compact solutions in consumer electronics.
The image set for a standard PFR project is derived from decapsulation of two samples, followed by scanning electron microscopy (SEM) analysis of a cross section of the power transistor die and optical analysis of the power transistor die delayered to the substrate or gate level. The PFR deliverable includes:

• Company Profile
• Executive Summary
• Downstream Identification (optional)
• Device Identification
• Process Analysis
• Layout Analysis
• Cost Analysis

The PFR deliverable provides competitive benchmarking information and enables cost-effective tracking of multiple competitors' technology.