This report presents a Logic Gate Utilization Analysis on Sony’s IMX214 CMOS image sensor (CIS) image signal processor (ISP). The IMX214 consists of Sony's 13 MP resolution Exmor RS™ high-dynamic ranger (HDR) stacked CIS. The image sensor comprises two dies, a pixel sensor CIS die and an image signal processor (ISP) die. The CIS and ISP dies are bonded together face-to-face to the printed wiring board (PWB) substrate forming one of Sony's stacked CIS. This report contains the following information:

Annotated die photograph highlighting the analyzed logic area

Sample images of filler cells and decoupling capacitors

Estimated logic gate area utilization results of the IMX214 ISP die