This report is a layout and design for manufacturability (DFM) feature analysis report of the Intel Xeon E3-1230V2 central processor unit (CPU) die. The Layout and DFM Feature Analysis Report uses primarily SEM analysis to examine the design rules and restrictive layout practices implemented in this technology. The narrative portion of the report comprises a die utilization analysis, layer-by-layer estimated design rule analysis, and a lithographic feature analysis. Mosaic images of several regions of the die are delivered in ICWorks Surveyor. ICWorks Surveyor allows clients to navigate all layers of a device to enable all aspects of Intel's layout methodologies to be understood.