The following is a CircuitVision Analysis of selected blocks on the Samsung Shannon 5100 5G modem. The report contains a full set of schematics and annotated photographs divided into the following sections:

• Architectural Overview
• Input Buffer
• Phase Locked Loop 1
• Phase-Locked loop 2
• DQ and DQS I/O Buffers
• SRAM Macro A
• SRAM Macro B
• SRAM Macro C
• SRAM Macro D
• Symbol Definitions
• Major Findings
• Standard Cells
• Appendix A - Signal List