Marvell 5nm Switch Handles 5G RAN
November 2, 2021 - Author: Bob Wheeler
Surprisingly, Marvell’s first Ethernet switch built in 5nm technology is for carrier access rather than data centers. Base stations, fronthaul gateways, and other equipment for 5G radio access networks (RANs), however, have thermal requirements that place a premium on low power dissipation. As a result, the company sampled the new 1.0Tbps Prestera DX7321 switch chip at the same time its 12nm predecessor moved to production. Compared with the DX7335, the 5nm design reduces power dissipation by 50% and package area by 25%. It sits in the middle of the DX73xx bandwidth range, with the family (code-named Aldrin3) spanning 200Gbps to 1,600Gbps.
Marvell designed the Prestera DX7321 for the first aggregation layer in the 5G RAN. In a fronthaul gateway, the chip carries 5G traffic between remote units (RUs) and distributed units (DUs). Current fronthaul optics allow up to 50Gbps over a single fiber/wavelength, connecting a radio head (RU) to the gateway. To handle existing LTE radio heads, customers can add an Octeon Fusion SoC to perform PHY-layer (L1) processing before the switch sends the 4G traffic to the remote baseband unit. At the point of presence (POP), a DX7335 switch can instead aggregate gateway traffic for transport over a 400G Ethernet metro ring.
The DX7321 also handles 400G Ethernet ports using 20x50Gbps PAM4 serdes. The chip’s 20 network ports handle all Ethernet rates from 1Gbps to 400Gbps. The DX73xx family includes 256-bit MACSec encryption on all ports, eliminating the need to add external PHYs for this feature. The chips also integrate Arm Cortex-M3-class CPUs to deliver real-time services such as timing protocols and telemetry. A PCIe Gen3 interface connects with external host processors.
Subscribers can view the full article in the Microprocessor Report.