What a Die-level Analysis Reveals About Apple's M5 Pro GPU Design

Apple's M5 Pro introduced one of the company's biggest architectural changes in recent years. Its new Fusion Architecture combines two silicon dies into a single system-on-chip (SoC), enabling unified memory and high-bandwidth communication across the package.

When Apple announced the processor, much of the discussion focused on how the two dies were connected and the role of TSMC's SoIC-X face-to-face (F2F) hybrid bonding technology. The next question is how Apple laid out the GPU die, which we examined in our latest Digital Floorplan Quick Look (DFQ).

Figure 1 – Apple M5 PRO SoC GPU: Digital Floorplan Quick Look Analysis (Source: TechInsights)

Packaging tells only part of the story

Fusion Architecture provides the foundation for the M5 Pro's unified SoC design. The processor integrates an 18-core CPU with 6 performance cores and 12 efficiency cores. Both the M5 Pro and M5 Max share the same CPU chiplet. The difference in performance lies in their respective GPUs, which enable the next-gen architecture introduced in M5 to scale up to 40 cores.

To understand how Apple achieved those capabilities, and the difference between the M5 Pro and Max, TechInsights looked beyond the package and into the GPU die itself. Completing a Digital Floorplan analysis for both GPU chiplets, in addition to analyzing the common CPU.

The Digital Floorplan Quick Look provides a detailed view of the GPU die through structural and layout analysis. It identifies the major functional blocks, measures how silicon area is allocated across logic, memory, analog, and I/O, and includes critical dimension measurements, foundry and process node identification, and manufacturing cost analysis. Providing insight into the design and process attributes that relate to device performance.

Supporting Competitive Design Analysis

The analysis supports multiple engineering workflows, including identifying process features and conducting competitive benchmarking. For foundries and semiconductor manufacturing teams, it illustrates the digital block layouts, structural features, and process characteristics that help characterize the implementation used on the device.

For fabless semiconductor companies and chip designers, it provides an independent view of Apple's design methodology. Highlighting architectural organization and design choices that support competitive product planning.

What's Included in the Full Digital Floorplan Analysis?

Building on TechInsights' earlier package analysis, the floorplan analysis provides a die-level view of Apple's latest GPU implementation, including:

• Teardown photographs, package photographs, X-rays, die markings, and die photographs
• Scanning electron microscopy (SEM) cross-sectional micrographs showing dielectric structures, major features, and transistor structures
• Measurements of key vertical and horizontal dimensions
• A plan-view optical micrograph delayered to the metal gate level
• Gate-level identification of major functional blocks
• Functional block size measurements and percentage die utilization
• High-resolution top metal and gate-level die photographs delivered through CircuitVision
• Manufacturing cost analysis based on the observed process