This report provides an analysis of the standard cells comprising about 70% of the area analyzed in the logic block of the HiSilicon Kirin 9000s (SMIC 7nm, n+2). Standard cells schematics are extracted to determine routing efficiency, gate density and global metal usage survey. GDSII files are generated from the extracted cells, providing insights into cell library benchmarking, routing and design rules, DTCO strategy and layout/local routing strategy.