This report presents a Digital Library Circuit Analysis of the standard logic of the AMD/ATI 215-0754009 Radeon HD5750 graphics processor, which is implemented in TSMC's 40 nm CMOS process. This report includes an image set of an area of the digital portion of the chip shot at polysilicon, metal 1, metal 2, and metal 3 layers. Approximately 5,000 digital standard cells are annotated and extracted. The report includes: ICWorks image database with images, annotations of placed cells, and all library cell schematics. A PDF report with: - library schematics - area percentage utilization, and gross and actual density for standard cells - identification of "filler" cells (decoupling capacitors, unconnected poly, etc) - cell track height - analysis of sequential logic versus combinatorial logic - Pareto chart of cell usage