Microprocessor Report
For more than 30 years, Microprocessor Report (MPR) has been the industry's go-to source for the latest microprocessor news. This subscriber-only publication covers a broad range of semiconductor topics. We publish an average of three new articles per week, each covering a new product, technology, or trend.
Our core coverage is of processors and SoCs for servers, PCs, supercomputers (HPC), smartphones, wearables, embedded systems, IoT devices, communications and networking equipment, and advanced automotive applications. We also cover licensable and open-source cores for CPU, DSP, graphics, and other functions. Many of our recent articles cover AI accelerators for cloud, edge, automotive, mobile, and IoT.
Deep Insight and In-Depth Analysis
Today's complex SoCs contain a variety of functions beyond the processor, so our coverage extends to wired and wireless communications protocols such as 5G, LTE, Ethernet, Wi-Fi, PON, PCI Express, and InfiniBand. We also cover special-purpose chips such as search engines, fabrics, silicon photonics, FPGAs, PHYs, cellular RF, high-bandwidth memory, and new memories such as Optane and NRAM.
We often write about new companies, new technologies, and new design approaches to keep our subscribers up to date on trends. We are particularly interested in new technologies for SoC design and manufacturing. We also keep an eye on mergers and acquisitions, and we use our in-house market-share data to highlight shifts in the market.
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Microprocessor Report
Blue Cheetah Connects Chiplets
Proprietary technology helps startup Blue Cheetah rapidly create custom die-to-die interconnects, including analog circuits, to attach chiplets. Focusing on the BoW standard, the company supports two fab processes.
Chiplets Ease Pain for Large Designs
Chiplet use is increasing, primarily for large in-house computing projects, but small chip designs don’t benefit. A broad third-party chiplet market remains years away.
TPUv4 Adds Large On-Chip Memory
The TPUv4 is now generally available through Google Cloud, although the company has used it internally for a year. The ASIC doubles the number of matrix units relative to the TPUv3.
N3E Will Be TSMC’s Main 3nm Node
TSMC’s enhanced 3nm process, N3E, employs fewer double-pattered EUV layers and allows more flexibility in the number of transistor fins than its predecessor, N3.
Eliyan Doubles UCIe Bandwidth
A serdes transceiver from Eliyan allows 32Gbps bidirectional chiplet signaling. It can reduce system cost in some systems by eliminating interposers or reduce power by halving speeds with no net bandwidth change.