SunLune Technology Jasmier X4 Ethereum Miner ASIC XMC 40nm CMOS Process Digital Floorplan Analysis
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This report provides an analysis of the floorplan design used in the SunLune Technology Jasmier X4 Ethereum Miner ASIC, fabricated on the XMC 40nm CMOS process, which incorporates DRAM DBI interconnect and includes an executive summary and supporting image sets SEM cross sectional and bevel imaging sets. The report provides process node and foundry identification, critical dimensions, functional and digital block summaries and gate count, memory block analysis.
