Marvell Adds Cores to Structera CXL

CXL stands out from a mix of interconnect standards, providing a way to connect memory to various processing elements and share memory resources within a data center. The latest to join the CXL 2.0 party is Marvell, which recently unveiled the Structera product line.
17Oct

Movellus Offers Core-level Dynamic Voltage Scaling

Movellus’s licensable Aeonic Power on-die voltage regulator technology enables dynamic voltage scaling circuity to be integrated in silicon at a core level, enabling fine-grained power control and the creation of virtual power islands around individual cores on the same chip.
01Oct

Tenstorrent Wormhole Upgrades Memory

Read our latest report on Tenstorrent's Wormhole architecture, covering the n150 and n300 PCIe boards, memory enhancements, performance boosts, and power efficiency. Discover how these innovations are influencing the AI-chip market and what lies ahead.
18Sep

Intel Talks 3nm at VLSI Conference

Intel is on track with its launch of five process nodes in four years—Intel 3 is the third. At the VLSI Symposium we had a good summary of Intel’s last FinFET node. It is now in full production of Xeon 6 processors in both Oregon and Ireland.
19Aug

Microprocessor Report July 2024 Review

Intel dominated industry news with Lunar Lake's AI capabilities and efficiency gains, while Raptor Lake devices received a fix for physical degradation; the month also saw major AI tool announcements and RISC-V product launches.
12Aug

Skymont Targets P-Core Parity

Intel’s Skymont CPU represents a significant evolution of the company’s efficiency cores from the origins of the Atom low-power core to something much closer in performance-per-clock to the company’s recent flagship performance cores.
05Aug