AMD plans a second generation of Versal AI Edge devices that integrate more CPUs with a more efficient hardware accelerator to bring more AI inference capability to edge applications.
NVIDIA’s Blackwell pods bring exascale compute to a rack while pushing the power envelope to 120 kW. The DGX GB200 NVL72 pod offers up to 1.44 ExaFLOPS of FP4 performance.
Cadence has updated its Vision DSP line to handle radar data types and instructions. It’s also offering an accelerator for high-FFT workloads such as 4D imaging radar.
NXP’s new S32N55, part of a new S32N processor family and the newly announced CoreRide brand, centralizes core driving functions that are currently implemented in localized ECUs.
Ambiq’s Apollo510 microcontroller pairs the company’s subthreshold energy-efficient design technology with vector acceleration performance to bring more AI capability to edge devices.
Renesas is testing demand for RISCV-based microcontrollers, introducing the first of what could be a series of such processors, the R9A02G021, targeting low-cost applications.
The new AI accelerator in Renesas’s RZ/V2H provides a boost in AI performance and efficiency to target high-performance robots that inhabit factory floors and smart homes and buildings.
NVIDIA has announced its Blackwell architecture, although the results are mixed. It is faster, but not as much so as the industry may have been expecting.
Microchip’s PIC16F13145 microcontroller includes a new configurable logic block that raises the amount of peripheral glue logic available by more than eight times compared with its predecessors.
Renesas and TSMC demonstrated two uses of fast MRAM at ISSCC. Renesas targets faster NVM; TSMC targets working memory. Their tradeoffs are very different.
With the expansion of the RA8 series, Renesas is integrating Arm’s highest-performing Cortex-M CPU in microcontrollers optimized for graphics display and motor control applications.
In the Meteor Lake CPU die, Intel has pushed the capacitance density of on-die capacitors to new heights by taking a page out of DRAM’s book of tricks.
Arm’s new Neoverse CSS N3 and CSS V3 provide a subsystem for N3 and V3 cores. For customers that won’t differentiate in that subsystem, the CSSs provide a head start.
The DA14592 is Renesas’s smallest multicore BLE SoC, featuring a power-thrifty radio transceiver that drops power by more than 23% for send and receive compared with Renesas’s other BLE chips.