Webinar - Memory Process and Integration Challenges: DRAM & NAND

Memory Process and Integration Challenges: DRAM & NAND

Tuesday, July 5 at 11:00 am (ET) or Wednesday, July 6 at 10:00 am (GMT+9)

In this Memory webinar, Dr. Jeongdong Choe will overview and discuss the latest memory technology trends and challenges, focusing on DRAM and NAND devices.

Note: Both sessions will include a live Question and Answer session with Dr. Choe.

Complete the form to register to attend the July 5, 2022 webinar.

Complete the form to register to attend the July 6, 2022 webinar.

DRAM cell scaling down to the 10 nm design rule (D/R) has been an ongoing development. Major DRAM players have been developing the next generations, so-called D1b, D1c, and beyond. Which means, DRAM cell D/R might be further scaled down to the single-digit nanometer era. Recently, DRAM cell scaling has slowed due to multiple challenges, including process integration, leakage, and sensing margin. Innovative technologies such as higher-k capacitor dielectric materials, pillar capacitors, recess channel transistors, and HKMG peripheral transistors can be seen in the most advanced DRAM products.

In the NAND space, manufacturers continue to race towards 3D NAND vertical gate numbers to increase storage density. They have planned the next 3D NAND products, including 232L/238L and more up to 4xxL or even 8xxL. To date, five different types of 3D NAND architectures are mainstream such as V-NAND, BiCS, CuA, 4D PUC, and Xtacking.

About the Speaker

Dr. Jeongdong Choe

Dr. Jeongdong Choe is a Senior Technical Fellow at TechInsights. He has over 30 years of hands-on experience in the semiconductor industry, R&D and reverse engineering analysis on DRAM, NAND/NOR FLASH, SRAM/Logic and Emerging Memory devices such as MRAM/STT-MRAM, PCRAM, XPoint, ReRAM and FeRAM. Dr. Choe worked for SK Hynix and Samsung Electronics for over 20 years. He has manufacturing and R&D expertise in high-technology, including direct experience in the semiconductor process flow, process integration, unit process and tools for photo-mask, photo-lithography, plasma/wet etching, CMP, deposition, implantation, diffusion and annealing.

After joining TechInsights, Dr. Choe focused on technology, device and architecture design analysis. He regularly publishes articles on semiconductor technology trends and roadmap. He also delivers annual memory seminars, memory technology updates, keynotes and talks at TechInsights on-/off-line seminars and global conferences.

Memory Process and Integration Challenges: DRAM & NAND
Don’t miss this webinar which will include a live Q&A session with Dr. Jeongdong Choe.

Register above today!

Memory eBook