Originally Presented: April 9, 2019 / 2:00pm to 3:00pm ET
Hosted By: Michel Roy
Low-density fan-out package technology has been around for more than a decade. Due to limitations in RDL counts and capabilities in line space / line width, this technology has traditionally been used in low-to-medium pin count applications, such as PMIC, audio codec, and RF devices.
TSMC were first to introduce a high-density wafer-based fan-out package technology solution, called Integrated Fan-Out (InFO). This technology targets higher pin count applications, such as application processors (AP). Apple was an early adopter of this new technology, first used in the A10 application processor of the iPhone 7, introduced in late 2016.
Samsung has recently introduced Fan Out Panel Level Packaging (FOPLP) technology. FOPLP is a high-density, panel-based fan-out package technology, which competes directly with TSMC’s InFO. Samsung first used the FOPLP in their latest Galaxy smartwatch, to co-package an AP die with a PMIC die.
In this webinar, we will look at the key structural elements of the two packaging solutions. Package cross-sections and RDL delayering images will be presented and discussed, which will provide attendees with an understanding of the proposed structures, and of the differences between the two technologies.
April 9, 2019
2:00pm to 3:00pm ET
Duration 1 Hour
About The Host
Expert who will be conducting this webinar
Senior Process Analysis Engineer
Michel holds the position of Senior Process Analysis Engineer at TechInsights. He provides technical support for patent licensing and patent evaluation based on reverse engineering output, as well as technical structural and material analysis of packages. He has over 25 years of professional experience in the semiconductor packaging industry, in package process engineering, package design engineering, package reliability and failure analysis.
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