Memory Technology Trend and Details: DRAM, NAND and Emerging Memory

DRAM cell scaling down to 16 nm design rule (D/R) has already been productized from major DRAM players such as Samsung, Micron and SK Hynix. They’re developing n+1 (15 nm) and n+2 (14 nm or beyond) so called 1z, 1a and 1b generation now, which means DRAM cell D/R might be able to further scale down to sub-14 nm without EUV adoption for DRAM cell patterning. The cell design scaling down is getting slower due to many scaling issues including patterning, leakage and sensing margin. Graphic DRAM and high bandwidth memories such as HBM2 and HMC2 adopted 20 nm or 10 nm-class DRAM technology nodes. Camera modules on smartphones have a triple-die structure by adding a low power DRAM die into the module. Some innovations such as higher-k dielectric materials, pillar capacitor and recess channel LV transistors can be seen in the advanced DRAM cell design. 

The race is on between major NAND manufacturers working to increase the number of vertical 3D NAND gates; they have all already introduced their own 9XL 3D NAND devices. Samsung 92L V-NAND (V5), Toshiba and Western Digital Company (WDC) 96L BiCS4, Intel/Micron 96L FG CuA, and SK Hynix 96L 4D NAND PUC products are on the market. Many innovative changes have been implemented compared with previous 3D NAND 64L and 72L/76L generation. Beyond storage density, 3D NAND is used for even the fastest SSDs, such as Samsung’s Z-SSD. The total number of vertical gates stacked is already over one hundred; for example, Toshiba has 109 gates and SK Hynix has 115 gates for their 96L 3D NAND products. Bit Density reached up to 6.53 Gb/mm² with QLC NAND design.  

Intel extends their XPoint memory application not only for conventional SSD but also DCPMM persistent memory, although Micron’s QuantX has been delayed. Everspin’s 3^rd generation STT-MRAM (pMTJ) and Adesto’s 2^nd generation ReRAM (CBRAM) technologies are on the market. 

In this presentation, we will discuss current and future DRAM, NAND and Emerging memory technology including process, design, and materials.  

Jeongdong Choe

Senior Technical Fellow, TechInsights

Dr. Jeongdong Choe is a Senior Technical Fellow at TechInsights. He has over 28 years of experience in the semiconductor industry, R&D and reverse engineering on DRAM, NAND/NOR FLASH, SRAM/Logic and Emerging memory. He worked for SK Hynix and Samsung Electronics for over 20 years. He joined TechInsights and has been focusing on technology analysis on semiconductor process, device and architecture. He has written many articles on memory/logic technology including DRAM comparison, 2D and 3D NAND details, and XPoint design and architecture. He quarterly produces and updates widely distributed memory roadmaps on DRAM, NAND and Emerging memory.