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The Advanced CMOS Essentials (ACE) deliverable for DRAM chips comprises a concise analyst’s summary document highlighting observed critical dimensions and salient features supported by the following image folders:
Downstream product teardown
Package X-rays, top metal and poly die photographs, non-invasive optical photos of die features
SEM bevel through the logic region and DRAM
SEM cross section of the general device structure, BEOL (metals, dielectrics) and FEOL structures
Two or three TEM cross sections, orthogonal to the word and bit lines, and possibly active directions of DRAM array, showing the DRAM capacitor array, lower metals and dielectrics, transistor gates, isolation, and other FEOL features
The results of TEM-EDS analyses are included in the ACE summary document. The ACE deliverable provides timely competitive benchmarking information and enables cost-effective tracking of technical innovation across a breadth of competitors.
This report presents an Advanced CMOS Essentials on the 20 nm process found in the SK Hynix H5AN8G8NAFR-UHC 8 Gb DDR4 SDRAM.