Product Item Code
HiSilicon Technologies Co. Ltd
Logic - Standard Cell GDS Analysis
This project presents a SoC Design Cell GDS analysis of the TSMC 7 nm (N7+ EUV) high-k metal (HKMG) CMOS process found in the HiSilicon Hi3690 Kirin 990 5G. This analysis is focused on the CPU area, implemented using a 7.5-track height library. We have selected multiple standard cells located in the CPU area and generated their layouts in a GDS format. The standard cell layouts are our interpretation of design intent and are redrawn based on a consistent set of design rules.
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