This project presents a SoC Design Analysis of the Apple A15 Bionic APL1W07 application processor, built in TSMC's N5 process. This analysis is focused on the CPU2 area, implemented using a 6-track height library. We have assessed the standard cell architecture by extracting and locating in the CPU2 layout multiple standard cells. We have extracted the routing density of the CPU2 digital logic library. Process and BEOL stack-up and utilization have also been analyzed.