Intel i3-8121U Cannon Lake Intel 10 nm SoC Overhead Layout Analysis DDR I/O to CPU Transition Region Standard Cell Essentials

Product Code
SCE-1805-801
Release Date
21/11/2018
Availability
Published
Product Item Code
INT-i3-8121U_die
Device Manufacturer
Intel
Device Type
Microprocessor
Subscription
Logic
Channel
Logic - Standard Cell Libraries
Report Code
SCE-1805-801
This project presents a Standard Cell Essentials Analysis of the Intel Cannon Lake i3-8121U DDR I/O region. It is a collection of scanning electron microscopy (SEM) montage images showing transition regions between an I/O IP block and a digital logic block, showcasing dummy structures and relationship to system-on-chip (SoC) design rules used on Intel Cannon Lake i3-8121U.
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