This report presents a power floorplan analysis (PFR) of the SanRex FMG50AQ120N6 1200 V 13 mOhm SiC power MOSFET. It features optimized conduction with 13 mOhm Rds(on) at a gate drive of Vgs = 20 V and low Rds(on) temperature dependency, increasing by only 2 mOhm up to 150 C, suitable for industrial applications and EV charging infrastructure.
The image set for a standard PFR project is derived from decapsulation of two samples, followed by scanning electron microscopy (SEM) analysis of a cross section of the power transistor die and optical analysis of the power transistor die delayered to the substrate or gate level. The PFR deliverable includes:

• Company Profile
• Executive Summary
• Downstream Identification (optional)
• Device Identification
• Process Analysis
• Layout Analysis
• Cost Analysis

The PFR deliverable provides competitive benchmarking information and enables cost-effective tracking of multiple competitors' technology.