This report presents a PMIC process analysis (PEF) of the NXP Semiconductors MC33FS4505NAE fail-silent safety power system basis chip. The NXP MC33FS4505NAE features an AEC-Q100 qualified PMIC using SMARTMOS process, targeting drive train electrification, safety and ADAS, and supports up to 40 V input, supplying MCU cores from 1 – 5 V and 0.5 – 2.2 A.
This report contains the following detailed information:

• Summary of observed device metrics and salient features
• Package optical photographs, package X-ray images, die photographs, optical photos of the die feature image set
• Plan-view images of the device delayered to the gate level
• Exploratory cross-sectional scanning electron microscope (SEM) images of the device structure
• Detailed cross-sectional scanning capacitance microscopy (SCM) and scanning microwave impedance microscopy (sMIM-C) analysis of the dopant structures
• Detailed cross-sectional transmission electron microscope (TEM and STEM) images of the power device structure
• Metal and dielectric layer composition identification based on TEM-EDS results

The image set for a standard PEF project is derived from a beveled sample for SEM planar analysis, one plane of cross-sectioning for SEM structural analysis, a single TEM sample for the detailed structural analysis, and planar and cross-sectional SCM and sMIM analysis. Value added information, such as additional planes of cross-sectioning, may be included on a case-by-case basis.
The Power Essentials deliverable provides basic competitive benchmarking information and enables cost-effective tracking of multiple competitors’ technology.