Product Code
SDA-2001-803
Availability
Published
Product Item Code
HPC-15-dy1973cl
Device Manufacturer
Hewlett-Packard
Device Type
Laptop Computer
Subscription
Logic
Channel
Logic - SoC Design Analysis (IP)
Logic - SoC Design Analysis
Intel 10 nm (2nd Gen) Ice Lake Overhead SoC Design Analysis
This report presents an SoC Design Analysis of the Intel i7-1065G7 (Ice Lake) SRG0N Thunderbolt 3 I/O logic region, built in Intel’s 10 nm 2nd Generation high-k metal gate (HKMG) FinFET CMOS process. It is a collection of SEM montage images showing the transition between an I/O IP block and a digital logic block, showcasing the relationship to system-on-chip (SoC) design rules used on the Intel i7-1065G7 (Ice Lake) SRG0N.
The report includes
The report includes
- Downstream product features and SoC-level areas of analysis
- Technology node contact and back-end-of-line (BEOL) process architecture assessment with stack up dimensions
- Features and dummy structures of the system-on-chip (SoC) design overhead associated with the transition between design IP blocks
- Scanning electron microscope (SEM) montage of a planar sample area delivered in CircuitVision
- Target areas are typically transitions between different types of IP blocks, such as analog I/O to digital, or to memory, and typically contain many dummy features
- Standard cell architecture by extraction and placement of multiple standard cells in the TB3 I/O logic layout
- Routing density of the TB3 I/O logic digital logic library
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