NVIDIA GV100-400-A1 TSMC 12FFN L1 Datapath Area Tensor Core D4 Standard Cell Essentials

Product Code

SCE-1809-801

Release Date

01/11/2018

Availability

Published

Product Item Code

NVI-GV100-400-A1

Device Manufacturer

nVIDIA

Device Type

Graphics Processor

Subscription

Logic

Channel

Logic - SoC Design Analysis (IP)

Logic - SoC Design Analysis

NVIDIA GV100-400-A1 TSMC 12FFN L1 Datapath Area Tensor Core D4 Standard Cell Essentials

This project presents a Standard Cell Essentials Analysis of the NVIDIA Titan V (GV100) application processor, built in TSMC’s 12 nm high-k metal gate (HKMG) finFET CMOS process. This analysis is focused on the tensor core area. We have assessed the standard cell architecture by extracting and locating in the tensor core layout multiple standard cells. We have extracted the routing density of the tensor core digital logic library. Process and back end of line (BEOL) stack-up and utilization have also been analyzed.

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