The specific analysis you need to stay competitive in this market
The SSD market is expected to grow from ~$35B in 2019 to ~$80B in 2025, driven by big-data, media, and enterprise applications. Migration from HDD to SSD continues as SSD capacities increase and price per bit continues to decrease.
The list of advantages associated with using SSD over HDD is growing alongside the popularity of SSD:
- Lower power usage when compared to HDD – typically less than ½ the power
- Less heat generated
- SSD are safe from magnetism, jolts, vibration
- Better reliability due to no moving parts
- Much lower latency which is important for performance sensitive or database environments (4-7ms HDD vs .05ms PCIe SSD)
- Sequential transfer rate (read/write): 255MBps HDD vs. up to 7,000 Mbps today
Storage Analysis Subscription
TechInsights provides custom analysis to address your specific storage analysis programs.
SSD capacities are being driven upward by two main innovations. Increasing the number of bits stored by each memory cell, and by stacking memory array layers (3D-NAND or V-NAND). Companies are shipping products today which support up to 4 bits per cell (Quad-Level-Cell) and up to 96 array layers with 128 layer architectures expected shortly.
While these approaches improve density, they also make it more challenging to use NAND due to read disturb errors, increasing bit error rates and reduced memory endurance. SSD memory controllers are key to advancing SSD performance, reliability, endurance and security. They have evolved to support faster host and flash interface standards. They are becoming more complex, incorporating innovative SSD administration and management algorithms, including error correction to address the challenges presented by 3D NAND and multi-level cell approaches. They are also incorporating advanced security features to protect user data.
SSD Flash Interface Functional Analysis Subscription
An SSD Flash Interface Functional Analysis captures power-up and data transfer activity on the memory channel signal lines connecting the flash memory controller to the flash memory (1)
The SSD is connected to host computer which is used to initiate drive operations and a logic analyzer captures waveforms during reading, writing and power-up. The resulting signal data is parsed into transaction tables to facilitate analysis. The analysis will show:
- Board level architecture between controller and memory
- Power up configuration behavior
- Proprietary command and addressing schemes
- Signal amplitude and timing
- Data transfer behavior (pipelining, block preparation, erase-on-fly)
- Data overwrite behavior
- Operational data rate
- Device polling status checks
This data is useful to companies trying to understand how others are addressing specific design challenges and to companies which have data transfer patents.
The technical analysis of the subscription will profile the interface transactions across in a range of SSDs released in late 2019 and later.
Flash Memory Interface – Program Command and Address Timing Diagrams
Flash Memory Interface – Excel transaction tables
A PDF report containing an architecture overview and test results are combined with .ala logic analyzer files for viewing timing diagrams and detailed Excel data transaction tables.