Agenda for Day Two: Wednesday November 2, 2022
9:00 – 9:50 AM
Keynote: How are power, cost and productivity limitations shaping the semiconductor industry?
Two generations of humans have witnessed twenty generations of semiconductor technology come and go. Like any real-world exponential, Moore’s self-fulfilling “Law” is inexorably flattening. This talk will examine how trends in silicon power, cost and productivity are coming together to drive new challenges and opportunities. With few silver bullets on the horizon, we will examine how the industry is pivoting to acknowledge – and exploit – these new realities.
9:50 – 10:10 AM
BREAK – Sponsored by Flex Logix
10:10 – 12:15 PM
Session 7: Chips for AI Acceleration
Both small and large semiconductor vendors are developing chips to deliver efficient AI performance. As the market matures, we see these vendors moving from simply offering high TOPS per watt to delivering complete hardware and software solutions that perform well on real-world neural networks. This session, led by TechInsights principal analyst Linley Gwennap, features chips for edge and data-center applications.
A Balanced Architecture for Future-Proof AI Acceleration at the Edge
Edge AI has been a hot topic for many years, but companies are now getting serious about deploying it. They’re recognizing the need to move from ‘toy’ models to leading-edge models that support higher accuracy and more functionality but require huge compute capability to run effectively. This presentation describes Kinara’s next-generation architecture, which supports much higher system-level performance than its predecessor, delivers increased flexibility for running newer models, and provides specialized encryption to protect customer’s model IP.
Tiny Spiking AI for Always-On Sensing
The brain relies on tiny spiking neural networks for sparse, robust, and energy-efficient processing of sensory data. This presentation discusses Innatera’s neuromorphic processing for always-on sensing applications. The company’s Spiking Neural Processor (SNP) implements a unique analog/mixed-signal architecture for energy-efficient inference of spiking neural networks, enabling full-featured AI applications with sub-milliwatt power and sub-millisecond latency. The presentation includes real-world application use cases and introduces Talamo, a powerful PyTorch-compatible SDK that radically simplifies application development.
Addressing deep-learning trends with Habana’s data-center accelerators
Deep-learning computation faces a growing number of challenges, which the industry and its players are working to address collectively and independently. With the increasing availability of resource-rich data and the growing demand for complex AI applications, compute capacity must increase while reducing model and application compute requirements. This presentation will discuss ways that Habana and its ecosystem partners are collaborating to speed time-to-model execution with greater ease for developers and data scientists.
High Performance from Cloud to Edge Inferencing
Natural Language Processing (NLP) models have become much larger in recent years and are projected to grow further. Common solutions for performing inference on these huge models involve expensive high-bandwidth memories and scale-out networking. This talk presents a low-cost solution that supports these workloads and offers the potential for super-linear performance improvements.
There will be Q&A and a panel discussion featuring above speakers.
12:15 – 1:45 PM
LUNCH Sponsored by Ceremorphic
1:45 – 3:45 PM
Session 8: CPU IP and GPU IP
Developers of SOCs for mobile, automotive, and data center applications need CPUs to handle computation and GPUs for rendering graphics. Designers increasingly are looking for scalable IP so that chips addressing different price points and power levels can share IP, accelerating chip design and simplifying software development. This session led by TechInsights Director of Market Analysis Joseph Byrne looks at new CPU IP and a low-power GPU capable of ray tracing.
Architecture and Key Features of SiFive's Newest Out-of-Order Vector Processor
Since launching the P650 RISC-V applications processor a year ago, SiFive has made continual product enhancements to the platform such as support for the RISC-V vector extension, multicluster, virtualization, and WorldGuard security. The result is a best-in-class RISC-V processor as demonstrated by industry-standard benchmarks such as SPECint that is ready to tackle challenging computing requirements in applications such as mobile, autonomous vehicles, and the data center. This next-generation processor, called the P670, will propel RISC-V from embedded applications to the forefront of computing, where raw performance is demanded. This presentation will step through the P670 architecture and key features. It is available to lead partners now and will be ready for general release in Q1 of 2023.
Andes Technology’s Next-Generation Scalable RISC-V Application Processor Family
Today, companies designing SoCs for cloud accelerators, enterprise storage systems, data-center networking equipment, and 5G infrastructure employ Andes vector processors to form large compute arrays or employ many instances of compact processors to handle partitioned channels. In this talk, Andes will describe its forthcoming next-generation RISC-V application processor family.
Power-Efficient Scalable Ray Tracing GPUs
Ray tracing has made a journey from non-real-time, compute-intensive systems, to real-time hybrid ones. Now, ray tracing is migrating from wall-plug-powered use cases (e.g., PC and console games) to battery-powered use cases that need to provide a compelling user experience within a constrained power envelope (e.g., mobile, AR, and automotive cases). Imagination will reveal the main aspects that need to be considered to create scalable ray tracing and how by using a hybrid rendering approach you can enhance the gaming experience with ray tracing while remaining in a mobile power budget.
Addressing Scalable Processor Performance in High-End Embedded Applications
Ever increasing performance requirements continuously fight the tight power and area constraints demanded by embedded applications. Coherent integration of real-time, application processors and specialized hardware accelerators as well as providing a wide range of memory and bandwidth options are critical to satisfying the implementation flexibility essential for SoC designers. This presentation will discuss a flexible processor architecture which can be configured from ultra-cost-effective to extreme performance, covering the broad gamut of high-end embedded application requirements.
There will be Q&A and a panel discussion featuring above speakers.
End of Conference
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