SK hynix 128L 3D PUC NAND (4D NAND)

SK hynix 128L 3D PUC NAND (4D NAND)

SK hynix has released the world’s first 128-layer (128L) 3D NAND, which they have termed 4D NAND. This is their second NAND generation built using Periphery Under Cell (PUC) architecture; the first was their 96L NAND.

In PUC architecture, peripheral circuits are stacked under the cell, resulting in higher 3D NAND bit density, and improving performance and capacity. This approach is comparable to Micron & Intel’s CuA (CMOS circuitry under cell array) and YMTC’s Xtacking (where peripheral circuitry and NAND array are processed separately and then hybrid bonded).

 

SK hynix 128L 3D PUC NAND (4D NAND) Analysis

Download TechInsights' SK hynix 128L PUC 3D NAND analysis, with a market overview, new technology overview, analysis details, and more.

 

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Based on our early analysis of this new technology, compared with the previous SK hynix 72L/76L P-BiCS and SK hynix 96L PUC, we observe the following:

  SK hynix 72L/76L P-BiCS SK hynix 96L PUC
(4D NAND 1st Gen.)
SK hynix 128L PUC
(4D NAND 2nd Gen.)
3D NAND Ver. V4 V5 V6
# Stack 2 2 2
# Total Gates Stacked 82 / 86
(excluding PCGs)
115 147
# Total Active WLs 72 / 76 96 128
# Selectors 3 SGSs + 3 SGDs 7 SGSs + 3 SGDs 7 SGSs + 3 SGDs
Vertical Cell Efficiency
(VCE)1
87.8 % / 88.4 % 83.5 % 87.1 %
Bit density 4.30 Gb/mm2 6.30 Gb/mm2 8.15 Gb/mm2 (expected)

1. VCE: % of # active cell among total gates, (# active WLs)/(#total gates)x100%

  • The 1st gen. 4D NAND PUC 96L products (V5) showed 115 gates in total on a silicon source plate
  • 2nd gen. PUC 128L products (V6) use 147 gates in total, likely including 9 dummy wordlines (DWLs), 7 select gates source side (SGS) and 3 select gates drain side (SGD)
  • This means vertical cell efficiency increased to 87.1 %, and memory bit density with around 8.15 Gb/mm2 expected on TLC die

The increase in bit density provided through the increase in layers (i.e. 76L to 96L and now to 128L) is pushing technology boundaries and will no doubt keep the competition on their toes. The increase in bit density also impacts other NAND memory design aspects which will become more challenging to address from scratch (i.e. without impartial third-party insight).

TechInsights expects to see ~128L offerings from all the major manufacturers in the coming months. We look forward to analyzing and comparing the different solutions.

 

 

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